For example, custom JTAG instructions can be provided to allow reading registers built from arbitrary sets of signals inside the FPGA, providing visibility for behaviors which are invisible to boundary scan operations.
The same JTAG techniques used to debug software running inside a CPU can help debug other digital design blocks inside an FPGA. Sometimes FPGA developers also use JTAG to develop debugging tools. Some toolchains can use ARM Embedded Trace Macrocell (ETM) modules, or equivalent implementations in other architectures to trigger debugger (or tracing) activity on complex hardware events, like a logic analyzer programmed to ignore the first seven accesses to a register from one particular subroutine. Most designs have “halt mode debugging”, but some allow debuggers to access registers and data buses without needing to halt the core being debugged. Data breakpoints are often available, as is bulk data download to RAM. One can set code breakpoints, both for code in RAM (often using a special machine instruction) and in ROM/flash. Processors can normally be halted, single stepped, or let run freely. The adoption of the JTAG standard helped move JTAG-centric debugging environments away from early processor-specific designs. There are many other such silicon vendor-specific extensions that may not be documented except under NDA. Some examples are ARM CoreSight and Nexus as well as Intel’s BTS (Branch Trace Storage), LBR (Last Branch Record), and IPT (Intel Processor Trace) implementations. Frequently individual silicon vendors however only implement parts of these extensions. Many silicon architectures such as PowerPC, MIPS, ARM, x86 built an entire software debug, instruction tracing, and data tracing infrastructure around the basic JTAG protocol.
System software debug support is for many software developers the main reason to be interested in JTAG. Those modules let software developers debug the software of an embedded system directly at the machine instruction level when needed, or (more typically) in terms of high level language source code. An in-circuit emulator (or, more correctly, a “JTAG adapter”) uses JTAG as the transport mechanism to access on-chip debug modules inside the target CPU. On most systems, JTAG-based debugging is available from the very first instruction after CPU reset, letting it assist with development of early boot software which runs before anything is set up.
Today JTAG is used as the primary means of accessing sub-blocks of integrated circuits, making it an essential mechanism for debugging embedded systems which might not have any other debug-capable communications channel. Although JTAG’s early applications targeted board level testing, here the JTAG standard was designed to assist with device, board, and system testing, diagnosis, and fault isolation.
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